The present invention relates generally to semiconductor memory, and more particularly to a test mode signal generator for a semiconductor memory device and a method of generating test mode signals.
A typical semiconductor memory device includes separate test circuits for testing the device in addition to the circuit unit that performs the primary functions of the semiconductor memory device. In a typical semiconductor device, testing is performed by inputting separate distinct test signals different from the general operation signals.
In order to improve test efficiency, a semiconductor memory will utilize various types of test modes (e.g., a test mode for voltage control and a test mode for data compression) and will include a test mode signal generator that generates signals for entering a specific test mode of these various test modes or for causing the entered test mode to be deactivated.
Generally, in a test mode signal generator, when a total of eleven addresses are inputted to a semiconductor memory, an address A<7> of the eleven addresses A<0:10> is used to generate a test mode register set signal TMRS together with a mode register set signal MRS, and addresses A<8:10> are used to generate a test mode set signal TMSET for informing of a test mode entry together with the test mode register set signal TMRS. The other addresses A<0:6> are used to code various test modes.
Referring to FIG. 1, a conventional test mode signal generator generates a test mode set signal TMSET which causes the semiconductor memory device to enter into a test mode. Additionally, the test mode signal generator generates a test mode signal TM (not shown) so that the semiconductor device performs a specific test designated by the test mode signal TM when the semiconductor memory enters the test mode.
In a conventional test mode signal generator, a test mode register set signal TMRS is inputted during three cycles in order to prevent the semiconductor memory from unintentionally entering into a test mode when noise or the like influences the device. A conventional test mode signal generator will activate the test mode set signal TMSET and output the activated test mode set signal TMSET when addresses A<8:10> corresponding to specific values known as predetermined test entry codes <H, H, L>, <L, H, H>, <H, L, L> are sequentially inputted during the respective cycles.
Further, a conventional test mode signal generator generates 128 test mode signals TM by decoding addresses A<0:6> and outputs a decoding signal as a test mode signal TM in response to the test mode set signal TMSET. The decoding signal is activated by decoding the addresses A<0:6> received during the respective cycles of the test mode register set signal TMRS for activating the test mode set signal TMSET.
In more detail, a conventional test mode signal generator includes latch circuits that latch 128 decoding signals for allowing the addresses A<0:6> to be decoded by the test mode set signal TMSET, and the conventional test mode signal generator generates a maximum of 128 test mode signals TM.
However, the complicated operations in a semiconductor memory device may require an increase in the number of test modes. In a conventional test mode signal generator, when the number of required test modes increases, the number of addresses necessary for supporting the increased number of test modes also increases.
Further, a latch circuit for latching an increased number of decoding signals will be necessary, and as a consequence the chip size increases.